"The project will build an intellectual property (IP) core for FPGA-based hardware of the soft-cancellation (SCAN) decoder for polar codes."

 Almost every digital communication system and data storage device now-a-days use error-correcting codes to increase the data rate and storage capacity, respectively. Error-correcting codes achieve high data rates and storage capacities by coping with the errors during communication and data write process in such systems. The next-generation terra-byte hard-disk drives and communication standards like 5G require high-throughput, low silicon area and power consumption from decoders of these error-correcting codes.

Currently, low-density parity-check (LDPC) and turbo codes dominate different communication standards and storage devices. However, with the stringent requirements of high-throughput, area- and power-efficient decoders for future systems, LDPC and turbo codes are usually hard to realize.

Polar codes are a recent breakthrough in coding theory as they perform close to LDPC and turbo codes but with a low-complexity encoder and decoder. The originally proposed decoder for polar codes was a hard-output decoder, not suitable to be used in iterative decoding architectures, which is the architecture employed in most of the systems today.

Our recent research proposed a low-complexity, high-throughput, soft-output decoder for polar codes. However, the performance metrics that matter to the system designer for different devices such as cell phones, hard-disk drives are the area utilization, power consumption and the throughput of the chip or hardware for the decoder. The next step for our research is to transform the gains of low-complexity and high-throughput to concrete numbers of area, power and throughput after realizing the hardware for the proposed soft-output decoder. The project also intends to propose any modifications necessary for increasing the throughput by finding possible parallelism in the decoding algorithm"